The present disclosure relates to a semiconductor structure, and particularly to a dynamic random access memory (DRAM) cell including a nanowire access transistor and a method of manufacturing the same.
Deep trench capacitors are used in a variety of semiconductor chips for high area capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from 4 fF (femto-Farad) to 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
As dimensions of semiconductor devices scale, semiconductor nanowire transistors with a wraparound gate structure are employed to provide enhanced gate control and lower leakage current over conventional field effect transistors. However, the integration of such semiconductor nanowire transistors with deep trench capacitors remains a challenge because a semiconductor nanowire inherently limits a contact area with any other structure because of the small lateral dimension of the semiconductor nanowire.